Generally, integrated circuits and other semiconductor devices are used in a variety of electronic applications, such as computers, cellular phones, personal computing devices, and many other applications. Home, industrial, and automotive devices, which in the past included only mechanical components, now have electronic parts that require semiconductor devices.
Semiconductor devices are manufactured by forming many different types of material layers over a semiconductor work-piece or wafer, and patterning the various material layers using lithography. The material layers typically include thin films of conductive, semiconductive, and insulating materials that are patterned and etched to form integrated circuits (IC's). There may be a plurality of transistors, memory devices, switches, conductive lines, diodes, capacitors, logic circuits, and other electronic components formed on a single die or chip.
Lithography involves the transfer of an image of a mask to a material layer of a die or chip, also referred to as a wafer. The image is formed as a network of pre-pattern openings in a layer of photoresist, the photoresist is developed, and the photoresist including the pre-pattern openings is used as a mask during a process to alter the material layer, such as by etching the material layer through the mask to thereby pattern the material layer.
Although various types of photolithographic processes are known in the art, state of the art semiconductor fabrication processes commonly use the 193 nm immersion photolithography to form the pre-pattern openings in the photoresist layer. The next generation lithography technology, “extreme” ultraviolet (EUV) photolithography, is planned to be used commercially after 2020. During semiconductor wafer fabrication, EUV light can be utilized in a lithographic process to enable transfer of very small patterns, such as nanometer-scale patterns, from an EUV lithographic mask (also referred to as an EUV “reticle” in the present application) to a photoresist layer disposed on a semiconductor wafer. A pattern formed on the EUV lithographic mask can be transferred to the photoresist layer by reflecting EUV light off of portions of a reflective surface upon which the EUV lithographic mask is disposed. However, due to the high energy of the EUV light, unwanted light can directly reach areas of the photoresist layer, thereby altering the pattern to be transferred by the mask. As such, patterning issues that are commonly known in the art and associated with EUV photolithography are the scatter of light as a function of density and change in density of light across a large distance.
As feature sizes of semiconductor devices continue to decrease, as is the trend in the semiconductor industry, transferring patterns from a lithography mask to a photoresist layer during fabrication of a semiconductor device becomes more difficult, due to the diffraction effects of the light or energy used to expose the photoresist. For example, during EUV photolithography, a reaction can occur that cleaves the link between the protecting groups and the photoresist material, resulting in shrinkage of the photoresist material. This reaction, and the associated photoresist shrinkage, is accelerated as the photoresist material is heated by the energy of the incident UV waves. Since the full thickness of the photoresist layer is targeted for stabilization, substantial mass loss, and shrinkage, can result from the exposure. Because the interface between the photoresist layer and substrate is constrained, the remainder of the photoresist layer shrinks in three dimensions. This leads to a phenomenon known as “pullback” where the top of the photoresist layer shrinks relative to the bottom. This effect is most pronounced on lithographic features such as contacts, line ends, and feature corners. The pullback phenomenon has undesired effects on the features, which make them unacceptable for device fabrication. This shrinkage occurs throughout the exposed regions of the photoresist layer and can cause deformation in the form of pullback on the upper portions of lithography features.
To compensate for the pullback effect, optical proximity corrections (OPC) are often made to lithography masks, which may involve adjusting the widths or lengths of the lines on the mask that are susceptible to the pullback effect. More advanced methods of OPC correct corner rounding and a general loss of fidelity in the shape of features by adding small secondary patterns, referred to as serifs, to the corners of patterns. The serifs, together with line width changes, enhance the amount of light transmitted through the transparent mask patterns.
As is currently known in the art, OPC methods are applied to a desired semiconductor design to allow the proper pattern to be realized on the silicon wafer using EUV photolithography. Semiconductor designs typically include a plurality of shapes to be drawn (and transferred to the wafer), for example a plurality of polygons. OPC methods computationally simulate the polygons and update the shape of each of the polygons with respect to how neighboring polygons will interact with such polygon, when the pattern is transferred to the photoresist layer using EUV photolithography.
One particular problem that has been encountered in the art of OPC and EUV photolithography is the so-called “tip-to-tip” printability problem, which is a direct result of the pullback effect and other proximity effects. Tip-to-tip printability issues arise in the context of printing neighboring polygons at or near the minimum dimensions allowable for the lithography process. As illustrated in FIG. 1, three circuits 100a, 100b, and 100c are presented. Circuit 100a represent a “normal” circuit wherein metal line features 101 and 102 of an upper metallization layer connect through vias 120 and a metal line feature 130 of a lower metallization layer to form a completed electrical circuit (shown by arrows 110). The tip-to-tip distance 105a between upper metallization layer metal line features 101 and 102 is defined as the distance between the closest (to one another) ends of the polygons that form the metal line features 101 and 102. Ideally, using EUV lithography, the resulting circuit printed on the semiconductor wafer would be substantially as presented with regard to circuit 100a. However, as is known in the art, the proximity effect may create printability problems wherein the idealized circuit 100a is not achieved with regard to the actual printing of metal line features 101 and 102. For example, as shown with respect to circuit 100b in FIG. 1, the tip-to-tip dimensions 105b have been unintentionally reduced to at or near zero due to EUV proximity problems, which results in a “short” in the electrical circuit 100b. As another example, as shown with respect to circuit 100c, the tip-to-tip dimensions 105c have been unintentionally increased such that the metal line features are not printed to overlie the vias 120, which results in a “disconnect” in the electrical circuit 100c. 
The above-described tip-to-tip printability problems encountered in the prior art are further illustrated in FIG. 2 for purposes of comparison with the inventive subject matter described herein (in FIG. 2, the term “tip-to-tip” is written as “T2T” for simplicity). For example, FIG. 2 illustrates a pattern set 200a that includes two mask polygons 211a and the resulting polygon shapes printed on a semiconductor wafer 212a that were created using the two mask polygons 211a. As shown, there is a “pullback” (shown by arrow 221) in the dimensions of the printed polygons 212a as compared to the dimensions of the mask polygons 211a. To correct for this problem using prior art OPC techniques, and with reference now to pattern set 200b, a bias (illustrated by arrow 222) may be added to the desired design polygons 213b, which results in extended polygons 211b when the mask is created. With the bias 222 to the mask polygons 211b, the printed polygons 212b have dimensions that more closely approximate the desired design polygons 213b. However, there is a limit to the closeness of the polygons in the mask, as required by mask rule checks (MRCs). To satisfy MRCs, a minimum distance must be maintained between mask features, as indicated by arrow 223 between mask polygons 211c in mask set 200c of FIG. 2. Thus, due to the bias that must be added, there is a dimensional design limit in the prior art (indicated by polygons 213c) that will satisfy the MRCs, resulting in a corresponding minimum dimension printability limit, indicated by arrow 224, for the printed polygons 212c. With ever decreasing feature sizes on integrated circuits, it would be desirable to find OPC techniques that are not so-constrained.
As such, it is desirable to provide improved OPC techniques for EUV lithography that address the foregoing tip-to-tip printability issue that have been encountered in the prior art. Furthermore, it is desirable to provide such techniques that do not require multiple masks, due the fact that the use of multiple masks would render EUV lithography financially uncompetitive against less expensive traditional lithography techniques (i.e., 193 nm lithography). Furthermore, other desirable features and characteristics of the inventive subject matter will become apparent from the subsequent detailed description of the inventive subject matter and the appended claims, taken in conjunction with the accompanying drawings and this background of the inventive subject matter.